On Sat, Oct 05, 2024 at 12:13:05PM +0530, Ram Kumar Dwivedi wrote:
> There are three algorithms supported for inline crypto engine:
> Floor based, Static and Instantaneous algorithm.
>
> Document the compatible used for the algorithm configurations
> for inline crypto engine found.
>
> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@xxxxxxxxxxx>
> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@xxxxxxxxxxx>
> Co-developed-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
> Signed-off-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 25a5edeea164..5ac56e164643 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -108,6 +108,11 @@ properties:
> description:
> GPIO connected to the RESET pin of the UFS memory device.
>
> + ice-config:
> + type: object
> + description:
> + ICE configuration table for Qualcom SOC
What goes in this node?
> +
> required:
> - compatible
> - reg
> @@ -350,5 +355,24 @@ examples:
> <0 0>,
> <0 0>;
> qcom,ice = <&ice>;
> +
> + ice_cfg: ice-config {
> + alg1 {
> + alg-name = "alg1";
> + rx-alloc-percent = <60>;
> + status = "disabled";
Examples should be enabled.
> + };
> +
> + alg2 {
> + alg-name = "alg2";
> + status = "disabled";
> + };
> +
> + alg3 {
> + alg-name = "alg3";
> + num-core = <28 28 15 13>;
> + status = "ok";
> + };
> + };
> };
> };
> --
> 2.46.0
>
