On Thu, Oct 03, 2024 at 07:29:02PM +0200, Angelo Dureghello wrote: > From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > There is a version of AXI DAC IP block (for FPGAs) that provides > a physical QSPI bus for AD3552R and similar chips, so supporting > spi-controller functionalities. > > For this case, the binding is modified to include some additional > properties. > > Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
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