On Fri, Sep 27, 2024 at 01:58:40PM +0200, Andrew Lunn wrote: > > I tried to setup an nfs server with a rootfs on my local network. I can > > mount it okay from my laptop so I think it is working okay. However, it > > does not seem to work on the lpi4a [3]. It appears the rgmii-id > > validation fails and the dwmac driver can not open the phy: > > > > thead-dwmac ffe7060000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 > > thead-dwmac ffe7060000.ethernet eth0: validation of rgmii-id with support \ > > 00,00000000,00000000,00006280 and advertisementa \ > > 00,00000000,00000000,00006280 failed: -EINVAL > > thead-dwmac ffe7060000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -22) > > Given what Emil said, i would suggest flipping the MDIO busses > around. Put the PHYs on gmac1's MDIO bus, and set the pinmux so that > its MDIO bus controller is connected to the outside world. Then, when > gmac1 probes first, its MDIO bus will be probed at the same time, and > its PHY found. > > Andrew I'm trying to configure the pinmux to have gmac1 control the mdio bus but it seems I've not done so correctly. I changed pins "GMAC0_MDC" and "GMAC0_MDIO" to function "gmac1" (see the patch below). I don't see any errors about the dwmac or phy in the boot log [1] but ultimately there is no carrier detected and the ethernet interface does not come up. Section "3.3.4.103 G3_MUXCFG_007" in the TH1520 System User Manual shows that bits [19:16] control GMAC0_MDIO_MUX_CFG where value of 2 selects GMAC1_MDIO. Similarly, bits [15:12] control GMAC0_MDC_MUX_CFG where a value of 2 also selects GMAC1_MDC. Emil - do you have any suggestion as to what I might be doing wrong with the pinmux? Thanks, Drew [1] https://gist.github.com/pdp7/1f9fcd76f26acd5715398d54f65a2e27 diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index ca84bc2039ef..f2f6c9d9b590 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ / { model = "Sipeed Lichee Module 4A"; compatible = "sipeed,lichee-module-4a", "thead,th1520"; + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; @@ -55,6 +60,22 @@ &sdio0 { status = "okay"; }; +&gmac0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_pins>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_pins>, <&mdio1_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + &gpio0 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -87,3 +108,101 @@ &gpio3 { "GPIO09", "GPIO10"; }; + +&mdio1 { + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins = "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins = "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + mdio1_pins: mdio1-0 { + mdc-pins { + pins = "GMAC0_MDC"; + function = "gmac1"; + bias-disable; + drive-strength = <13>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdio-pins { + pins = "GMAC0_MDIO"; + function = "gmac1"; + bias-disable; + drive-strength = <13>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +};
