In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameters for
High Speed Mode") hs_hcnt and hs_lcnt are computed based on fixed tHIGH = 160
and tLOW = 320. However, the set of these fixed values only applies to the
combination of hardware parameters "IC_CAP_LOADING = 400pF" and
"IC_FREQ_OPTIMIZATION = 1". Outside of this combination, SCL frequency may not
reach 3.4 MHz if hs_hcnt and hs_lcnt are both computed using these two fixed
values.
Since there are no any registers controlling these two hardware parameters,
their values can only be declared through the device tree.
v2:
- provide more hardware information in dt-bindings
- rename "bus-loading" to "bus-capacitance-pf"
- call new i2c_dw_fw_parse_hw_params() in i2c_dw_fw_parse_and_configure() to
parse hardware parameters from the device tree.
Michael Wu (2):
dt-bindings: i2c: snps,designware-i2c: add bus-capacitance-pf and
clk-freq-optimized
i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters
.../bindings/i2c/snps,designware-i2c.yaml | 14 ++++++++++++++
drivers/i2c/busses/i2c-designware-common.c | 16 ++++++++++++++++
drivers/i2c/busses/i2c-designware-core.h | 6 ++++++
drivers/i2c/busses/i2c-designware-master.c | 14 ++++++++++++--
4 files changed, 48 insertions(+), 2 deletions(-)
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2.43.0
