On Thu, Sep 26, 2024 at 4:33 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > > Il 25/09/24 12:57, Fei Shao ha scritto: > > There are two hardware IP blocks in MT8188 video decoder pipeline: > > vdec-lat and vdec-core, which are powered by vdec0 and vdec1 power > > domains respectively. > > > > We noticed that vdec-core needs to be powered down before vdec-lat > > during suspend to prevent failures. It's unclear if it's an intended > > hardware design or due to power isolation glitch. But in any case, we > > observed a power-off sequence here, and it can be considered as an > > indirect dependency implication between the vdec0 and vdec1 domains. > > > > Given that, update vdec1 as a sub-domain of vdec0 to enforce the > > sequence. Also, use more specific clock names for both power domains. > > > > As far as I know, yes, there is a sequence: > - Cores (mtk-vcodec-core) gets suspended first > - Then the LATs gets suspended (mtk-vcodec-lat) > - Finally, the LAT SoC gets suspended (mtk-vcodec-lat-soc) > > ...but you checked that downstream, and your downstream misses the lat-soc HW > instance, and only has the lat one. > > Are you sure that this is not the reason why you're getting this issue? :-) > > Otherwise, I feel like we must ask for some clarification from MediaTek, as > I'm mostly sure that the two cores are independent from each other (but I > might, of course, be wrong!). Yes I think I should... this is actually based on a downstream patch of theirs. My understanding is that LAT SoC is not always in the vdec pipeline for every MediaTek SoCs. Although the MT8188 and MT8195 have much in common, I have a vague impression that MT8188 doesn't have a LAT SoC HW, so the downstream video decoding works smoothly without describing that in DT... but still, I could be wrong, and things just happen to work. Anyway, I'll find someone on the MediaTek side for clarification. The datasheet I have doesn't seem to contain such information. Regards, Fei > > Cheers, > Angelo
