In MediaTek PCIe gen3 bindings, "clocks" accepts a range of 1-6 clocks
across all SoCs. But in practice, each SoC requires a particular number
of clocks as defined in "clock-names", and the length of "clocks" and
"clock-names" can be inconsistent with current bindings.
For example:
- MT8188, MT8192 and MT8195 all require 6 clocks, while the bindings
accept 4-6 clocks.
- MT7986 requires 4 clocks, while the bindings accept 4-6 clocks.
Update minItems and maxItems properties for individual SoCs as needed to
only accept the correct number of clocks.
Fixes: c6abd0eadec6 ("dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581")
Signed-off-by: Fei Shao <fshao@xxxxxxxxxxxx>
---
.../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 898c1be2d6a4..f05aab2b1add 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -149,7 +149,7 @@ allOf:
then:
properties:
clocks:
- minItems: 4
+ minItems: 6
clock-names:
items:
@@ -178,7 +178,7 @@ allOf:
then:
properties:
clocks:
- minItems: 4
+ minItems: 6
clock-names:
items:
@@ -207,6 +207,7 @@ allOf:
properties:
clocks:
minItems: 4
+ maxItems: 4
clock-names:
items:
--
2.46.0.792.g87dc391469-goog
