During inspecting dtbs_check errors, we found the power domain setting of DPI node "dp_intf0" is missing. Add power domain setting to "MT8195_POWER_DOMAIN_VDOSYS0" for "dp_intf0" Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> Signed-off-by: Tommy Chen <tommyyl.chen@xxxxxxxxxxxx> Signed-off-by: Macpaul Lin <macpaul.lin@xxxxxxxxxxxx> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+) Changes for v1: - This patch is related to adding mt8195-dp-intf to DT schema fix for - http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml - patch: https://lore.kernel.org/all/20240924103156.13119-6-macpaul.lin@xxxxxxxxxxxx/ Changes for v2: - Fix typo for Tommy's email address. Others remains no change. Changes for v3: - Added Suggested-by: and Reviewed-by: tags. Thanks! diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ade685ed2190..6218bd7abb05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3252,6 +3252,7 @@ dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c015000 0 0x1000>; interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, <&vdosys0 CLK_VDO0_DP_INTF0>, <&apmixedsys CLK_APMIXED_TVDPLL1>; -- 2.45.2
