On Tue, 24 Sept 2024 at 14:31, Mahadevan P <quic_mahap@xxxxxxxxxxx> wrote:
>
>
> On 9/24/2024 5:46 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 04:42:02PM GMT, Mahadevan P wrote:
> >> On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
> >>> On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
> >>>> Add definitions for the display hardware used on the
> >>>> Qualcomm SA8775P platform.
> >>>>
> >>>> Signed-off-by: Mahadevan <quic_mahap@xxxxxxxxxxx>
> >>>> ---
> >>>> .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++++++++++++++++++
> >>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-
> >>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +-
> >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
> >>>> 4 files changed, 491 insertions(+), 3 deletions(-)
> >>>> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> >>>>
> > [...]
> >
> >>>> +static const struct dpu_intf_cfg sa8775p_intf[] = {
> >>>> + {
> >>>> + .name = "intf_0", .id = INTF_0,
> >>>> + .base = 0x34000, .len = 0x280,
> >>>> + .features = INTF_SC7280_MASK,
> >>>> + .type = INTF_DP,
> >>>> + .controller_id = MSM_DP_CONTROLLER_0,
> >>>> + .prog_fetch_lines_worst_case = 24,
> >>>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> >>>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> >>>> + }, {
> >>>> + .name = "intf_1", .id = INTF_1,
> >>>> + .base = 0x35000, .len = 0x300,
> >>>> + .features = INTF_SC7280_MASK,
> >>>> + .type = INTF_DSI,
> >>>> + .controller_id = MSM_DSI_CONTROLLER_0,
> >>>> + .prog_fetch_lines_worst_case = 24,
> >>>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> >>>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> >>>> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> >>>> + }, {
> >>>> + .name = "intf_2", .id = INTF_2,
> >>>> + .base = 0x36000, .len = 0x300,
> >>>> + .features = INTF_SC7280_MASK,
> >>>> + .type = INTF_DSI,
> >>>> + .controller_id = MSM_DSI_CONTROLLER_1,
> >>>> + .prog_fetch_lines_worst_case = 24,
> >>>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> >>>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> >>>> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> >>>> + }, {
> >>>> + .name = "intf_3", .id = INTF_3,
> >>>> + .base = 0x37000, .len = 0x280,
> >>>> + .features = INTF_SC7280_MASK,
> >>>> + .type = INTF_NONE,
> >>>> + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> >>>> + .prog_fetch_lines_worst_case = 24,
> >>>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> >>>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> >>>> + }, {
> >>>> + .name = "intf_4", .id = INTF_4,
> >>>> + .base = 0x38000, .len = 0x280,
> >>>> + .features = INTF_SC7280_MASK,
> >>>> + .type = INTF_DP,
> >>>> + .controller_id = MSM_DP_CONTROLLER_1,
> >>>> + .prog_fetch_lines_worst_case = 24,
> >>>> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> >>>> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
> >>>> + }, {
> >>> Where is intf_5 ?
> >>
> >> intf_5 of base address 0x39000 is not supported on this target.
> > Not supported by whom?
>
>
> In sa8775p mdss architecture intf_5 is not present. So we are not adding
> in SW too.
ack, thanks for the explanation. It's better now.
--
With best wishes
Dmitry
