Include the 'clocks' and 'clock-names' properties in the AXI Quad-SPI bindings. When the AXI4-Lite interface is enabled, the core operates in legacy mode, maintaining backward compatibility with version 1.00, and uses 's_axi_aclk' and 'ext_spi_clk'. For the AXI interface, it uses 's_axi4_aclk' and 'ext_spi_clk'. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xxxxxxx> --- BRANCH: for-next --- .../devicetree/bindings/spi/spi-xilinx.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml index 4beb3af0416d..9dfec195ecd4 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml @@ -12,6 +12,25 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,axi-quad-spi-1.00.a + then: + properties: + clock-names: + items: + - const: s_axi_aclk + - const: ext_spi_clk + + else: + properties: + clock-names: + items: + - const: s_axi4_aclk + - const: ext_spi_clk + properties: compatible: enum: @@ -25,6 +44,12 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + xlnx,num-ss-bits: description: Number of chip selects used. minimum: 1 @@ -39,6 +64,8 @@ required: - compatible - reg - interrupts + - clocks + - clock-names unevaluatedProperties: false @@ -49,6 +76,8 @@ examples: interrupt-parent = <&intc>; interrupts = <0 31 1>; reg = <0x41e00000 0x10000>; + clocks = <&clkc 72>, <&clkc 73>; + clock-names = "s_axi4_aclk", "ext_spi_clk"; xlnx,num-ss-bits = <0x1>; xlnx,num-transfer-bits = <32>; }; -- 2.34.1