From: Chuan Liu <chuan.liu@xxxxxxxxxxx> Add the PLL clock controller dt-bindings for Amlogic A5 SoC family. Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx> Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx> --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 62 ++++++++++++++++++++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..ef9e40193a1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu <chuan.liu@xxxxxxxxxxx> + - Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx> + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator (usually at 24MHz) + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal_24m + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@8000 { + compatible = "amlogic,a5-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1a4>; + clocks = <&xtal_24m>, + <&scmi_clk 6>, + <&scmi_clk 7>; + clock-names = "xtal_24m", + "fix_dco", + "fix"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@xxxxxxxxxxx> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ -- 2.37.1
