Use the newly introduced macros instead of raw number. With this device
tree code is a bit easier to understand.
Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
---
arch/arm/boot/dts/microchip/sam9x60.dtsi | 18 +++++++++---------
arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++--------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 04a6d716ecaf..eeda277e684f 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -560,7 +560,7 @@ tcb0: timer@f8008000 {
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k SCKC_MD_SLCK>;
clock-names = "t0_clk", "slow_clk";
};
@@ -570,7 +570,7 @@ tcb1: timer@f800c000 {
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k SCKC_MD_SLCK>;
clock-names = "t0_clk", "slow_clk";
};
@@ -1038,7 +1038,7 @@ hlcdc: hlcdc@f8038000 {
compatible = "microchip,sam9x60-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k SCKC_TD_SLCK>;
clock-names = "periph_clk","sys_clk", "slow_clk";
assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
@@ -1313,20 +1313,20 @@ pmc: clock-controller@fffffc00 {
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
#clock-cells = <2>;
- clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+ clocks = <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal>;
clock-names = "td_slck", "md_slck", "main_xtal";
};
reset_controller: reset-controller@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
};
shutdown_controller: poweroff@fffffe10 {
compatible = "microchip,sam9x60-shdwc";
reg = <0xfffffe10 0x10>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
#address-cells = <1>;
#size-cells = <0>;
atmel,wakeup-rtc-timer;
@@ -1338,7 +1338,7 @@ rtt: rtc@fffffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k 1>;
+ clocks = <&clk32k SCKC_TD_SLCK>;
};
pit: timer@fffffe40 {
@@ -1364,14 +1364,14 @@ rtc: rtc@fffffea8 {
compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
reg = <0xfffffea8 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k 1>;
+ clocks = <&clk32k SCKC_TD_SLCK>;
};
watchdog: watchdog@ffffff80 {
compatible = "microchip,sam9x60-wdt";
reg = <0xffffff80 0x24>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index 17bcdcf0cf4a..2efca9838d69 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -246,7 +246,7 @@ pmc: clock-controller@e0018000 {
reg = <0xe0018000 0x200>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <2>;
- clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+ clocks = <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal>;
clock-names = "td_slck", "md_slck", "main_xtal";
};
@@ -254,13 +254,13 @@ reset_controller: reset-controller@e001d000 {
compatible = "microchip,sama7g5-rstc";
reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
#reset-cells = <1>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
};
shdwc: poweroff@e001d010 {
compatible = "microchip,sama7g5-shdwc", "syscon";
reg = <0xe001d010 0x10>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
#address-cells = <1>;
#size-cells = <0>;
atmel,wakeup-rtc-timer;
@@ -272,7 +272,7 @@ rtt: rtc@e001d020 {
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xe001d020 0x30>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk32k 1>;
+ clocks = <&clk32k SCKC_TD_SLCK>;
};
clk32k: clock-controller@e001d050 {
@@ -291,14 +291,14 @@ rtc: rtc@e001d0a8 {
compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
reg = <0xe001d0a8 0x30>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk32k 1>;
+ clocks = <&clk32k SCKC_TD_SLCK>;
};
ps_wdt: watchdog@e001d180 {
compatible = "microchip,sama7g5-wdt";
reg = <0xe001d180 0x24>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk32k 0>;
+ clocks = <&clk32k SCKC_MD_SLCK>;
};
chipid@e0020000 {
@@ -312,7 +312,7 @@ tcb1: timer@e0800000 {
#size-cells = <0>;
reg = <0xe0800000 0x100>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k SCKC_TD_SLCK>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -906,7 +906,7 @@ tcb0: timer@e2814000 {
#size-cells = <0>;
reg = <0xe2814000 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k SCKC_TD_SLCK>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
--
2.39.2
