Hi Prabhakar,
On Tue, Jul 30, 2024 at 2:26 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> This patch series aims to correct GICD and GICR sizes on RZ/G2L(LC),
> RZ/G2UL, RZ/V2L and RZ/G3S SoCs. These SoCs are equipped with GIC-600.
>
> GIC-600 supports MBI by default, so GICD size is set to 128kB.
> On RZ/G2UL and RZ/G3S SoC despite being single core the GICR size is set
> to 256kB as dumping the GICR_IIDR register shows it has two instances of
> GICR.
>
> v1->v2
> - Dropped changes for single core
> - Updated commit message
Thanks for your series!
I have to trust you on this, and will queue this series in
renesas-devel for v6.12, with s/kB/KiB/g.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
