On Thu, Aug 22, 2024 at 06:27:51PM +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > Document the Renesas RZ/G3S USB PHY Control IP. This is similar with the > one found on the RZ/G2L SoC the exception being that the SYSC USB specific > signal need to be configured before accessing the USB area. This is > done though a reset signal. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
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