Hi Peter,
On Tue, 2024-08-20 at 18:29 +0800, Peter Yin wrote:
> From: Peter Yin <peter.yin@xxxxxxxxxxxx>
>
> power-card-enable
> uart-switch-button
> power-fault-n
> asic0-card-type-detection0-n
> asic0-card-type-detection1-n
> asic0-card-type-detection2-n
> uart-switch-lsb
> uart-switch-msb
>
> Signed-off-by: Peter Yin <peteryin.openbmc@xxxxxxxxx>
Can you please your author email consistent with your Signed-off-by
email? Currently this generates a checkpatch warning:
Executing: ./scripts/checkpatch.pl --strict -g HEAD
WARNING: From:/Signed-off-by: email address mismatch: 'From: Peter Yin <peter.yin@xxxxxxxxxxxx>' != 'Signed-off-by: Peter Yin <peteryin.openbmc@xxxxxxxxx>'
Thanks,
Andrew
> ---
> .../dts/aspeed/aspeed-bmc-facebook-harma.dts | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
> index 92068c65eae4..9db95a791128 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
> @@ -566,7 +566,7 @@ &gpio0 {
> /*B0-B7*/ "","","","",
> "bmc-spi-mux-select-0","led-identify","","",
> /*C0-C7*/ "reset-cause-platrst","","","","",
> - "cpu0-err-alert","","",
> + "cpu0-err-alert","power-card-enable","",
> /*D0-D7*/ "","","sol-uart-select","","","","","",
> /*E0-E7*/ "","","","","","","","",
> /*F0-F7*/ "","","","","","","","",
> @@ -585,7 +585,9 @@ &gpio0 {
> /*O0-O7*/ "","","","","","","","",
> /*P0-P7*/ "power-button","power-host-control",
> "reset-button","","led-power","","","",
> - /*Q0-Q7*/ "","","","","","power-chassis-control","","",
> + /*Q0-Q7*/
> + "","","","",
> + "","power-chassis-control","","uart-switch-button",
> /*R0-R7*/ "","","","","","","","",
> /*S0-S7*/ "","","","","","","","",
> /*T0-T7*/ "","","","","","","","",
> @@ -685,7 +687,7 @@ &sgpiom0 {
> "FM_BOARD_REV_ID2","",
> "FM_BOARD_REV_ID1","",
> /*H0-H3 line 112-119*/
> - "FM_BOARD_REV_ID0","",
> + "FM_BOARD_REV_ID0","reset-control-cmos-clear",
> "","","","","","",
> /*H4-H7 line 120-127*/
> "","",
> @@ -716,9 +718,15 @@ &sgpiom0 {
> "cpu0-thermtrip-alert","",
> "reset-cause-pcie","",
> /*L4-L7 line 184-191*/
> - "pvdd11-ocp-alert","","","","","","","",
> + "pvdd11-ocp-alert","",
> + "power-fault-n","",
> + "asic0-card-type-detection0-n","",
> + "asic0-card-type-detection1-n","",
> /*M0-M3 line 192-199*/
> - "","","","","","","","",
> + "asic0-card-type-detection2-n","",
> + "uart-switch-lsb","",
> + "uart-switch-msb","",
> + "","",
> /*M4-M7 line 200-207*/
> "","","","","","","","",
> /*N0-N3 line 208-215*/
