The common PLL clock controller in Qualcomm IPQ chipsets provides
the clocks to the networking hardware blocks that are internal or
external to the SoC. This driver configures the common PLL clock
controller to enable the output clocks to such networking hardware
blocks. These networking blocks include the internal PPE (Packet
Process Engine), external connected Ethernet PHY, or external switch.
The controller expects the input reference clock from the internal
Wi-Fi block acting as the clock source. The output clocks supplied
by the controller are fixed rate clocks.
The driver is being enabled to support IPQ9574 SoC initially, and
will be extended for other SoCs.
Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
---
Luo Jie (4):
dt-bindings: clock: qcom: Add common PLL clock controller for IPQ SoC
clk: qcom: Add common PLL clock controller driver for IPQ SoC
arm64: defconfig: Enable Qualcomm IPQ common PLL clock controller
arm64: dts: qcom: Add common PLL node for IPQ9574 SoC
.../bindings/clock/qcom,ipq-cmn-pll.yaml | 87 ++++++++
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 +-
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-ipq-cmn-pll.c | 233 +++++++++++++++++++++
7 files changed, 358 insertions(+), 2 deletions(-)
---
base-commit: 222a3380f92b8791d4eeedf7cd750513ff428adf
change-id: 20240808-qcom_ipq_cmnpll-7c1119b25037
Best regards,
--
Luo Jie <quic_luoj@xxxxxxxxxxx>
