On Thu, Aug 08, 2024 at 10:22:27AM +0530, Manorit Chawdhry wrote: > Hi Nishanth, > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > > new file mode 100644 > > > index 000000000000..2ea470d1206d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > > > @@ -0,0 +1,21 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only OR MIT > > > +/* > > > + * Device Tree Source for J784S4 SoC Family Main Domain peripherals > > > + * > > > + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ > > > + */ > > > + > > > +&cbass_main { > > > + c71_3: dsp@67800000 { > > > + compatible = "ti,j721s2-c71-dsp"; > > > + reg = <0x00 0x67800000 0x00 0x00080000>, > > > + <0x00 0x67e00000 0x00 0x0000c000>; > > > + reg-names = "l2sram", "l1dram"; > > > + ti,sci = <&sms>; > > > + ti,sci-dev-id = <40>; > > > + ti,sci-proc-ids = <0x33 0xff>; > > > + resets = <&k3_reset 40 1>; > > > + firmware-name = "j784s4-c71_3-fw"; > > > + status = "disabled"; > > > + }; > > > +}; > > > > I am looking at https://www.ti.com/lit/ug/spruje3/spruje3.pdf (page 26), > > Device Comparison: > > > > CPSW/Serdes, PCIE is also different? Was that missed? > > I had talked to Siddharth in the past regarding that and he had > mentioned that no change would be required with the previous patchsets > that I had shared, adding him to the thread Manorit, Since J784S4-EVM enables only PCIe0 and PCIe1 which matches the instances enabled/supported on J742S2-EVM, I had informed you that for the purpose of validation, no changes will be required w.r.t. PCIe, if k3-j742s2-evm.dts is including k3-j784s4-evm.dts. However, considering that the device-tree should describe the hardware, when upstreaming the device-tree for J742S2, PCIe2 and PCIe3 should be deleted (if k3-j784s4-evm.dts is included by k3-j742s2-evm.dts) OR dropped (if there is a "common" file that is used to describe the peripherals common to J742S2 and J784S4 as done in the current series). Also, SERDES2 is not present on J742S2 SoC while J784S4 has SERDES0, SERDES1, SERDES2 and SERDES4. There is no difference w.r.t. CPSW9G in terms of the CPSW9G instance itself, but the difference is that CPSW9G cannot use SERDES2. So CPSW9G can only be used with SERDES4 on J742S2 SoC, but J742S2-EVM has the SERDES4 lines connected to Display Ports, due to which CPSW9G is essentially non-functional on J742S2-EVM. Regards, Siddharth.
