On Sat, 3 Aug 2024, Krishna chaitanya chundru wrote: > QPS615 is the PCIe switch which has one upstream and three downstream > ports. One of the downstream ports is used as endpoint device of Ethernet > MAC. Other two downstream ports are supposed to connect to external > device. One Host can connect to QPS615 by upstream port. > > QPS615 switch power is controlled by the GPIO's. After powering on > the switch will immediately participate in the link training. if the > host is also ready by that time PCIe link will established. > > The QPS615 needs to configured certain parameters like de-emphasis, > disable unused port etc before link is established. > > The device tree properties are parsed per node under pci-pci bridge in the > devicetree. Each node has unique bdf value in the reg property, driver > uses this bdf to differentiate ports, as there are certain i2c writes to > select particulat port. > > As the controller starts link training before the probe of pwrctl driver, > the PCIe link may come up before configuring the switch itself. > To avoid this introduce two functions in pci_ops to start_link() & > stop_link() which will disable the link training if the PCIe link is > not up yet. ??? This paragraph contradicts with itself. First it says link training starts and the link may come up, and then it says opposite, that is, disable the link training if the link is not up yet. So which way it is? If link can come up, why do you need to disable link training at all? Cannot you just trigger another link training after the configuration has been done so the new configuration is captured? If not, why? -- i. > Now PCI pwrctl device is the child of the pci-pcie bridge, if we want > to enable the suspend resume for pwrctl device there may be issues > since pci bridge will try to access some registers in the config which > may cause timeouts or Un clocked access as the power can be removed in > the suspend of pwrctl driver. > > To solve this make PCIe controller as parent to the pci pwr ctrl driver > and create devlink between host bridge and pci pwrctl driver so that > pci pwrctl driver will go suspend only after all the PCIe devices went > to suspend. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > --- > Changes in V1: > - Fix the code as per the comments given. > - Removed D3cold D0 sequence in suspend resume for now as it needs > seperate discussion. > - change to dt approach for configuring the switch instead of request_firmware() approach > - Link to v1: https://lore.kernel.org/linux-pci/20240626-qps615-v1-4-2ade7bd91e02@xxxxxxxxxxx/T/ > --- > > --- > Krishna chaitanya chundru (8): > dt-bindings: PCI: Add binding for qps615 > dt-bindings: trivial-devices: Add qcom,qps615 > arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615 > PCI: Change the parent to correctly represent pcie hierarchy > PCI: Add new start_link() & stop_link function ops > PCI: dwc: Add support for new pci function op > PCI: qcom: Add support for host_stop_link() & host_start_link() > PCI: pwrctl: Add power control driver for qps615 > > .../devicetree/bindings/pci/qcom,qps615.yaml | 191 ++++++ > .../devicetree/bindings/trivial-devices.yaml | 2 + > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 ++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > drivers/pci/bus.c | 3 +- > drivers/pci/controller/dwc/pcie-designware-host.c | 18 + > drivers/pci/controller/dwc/pcie-designware.h | 16 + > drivers/pci/controller/dwc/pcie-qcom.c | 39 ++ > drivers/pci/pwrctl/Kconfig | 7 + > drivers/pci/pwrctl/Makefile | 1 + > drivers/pci/pwrctl/core.c | 9 +- > drivers/pci/pwrctl/pci-pwrctl-qps615.c | 638 +++++++++++++++++++++ > include/linux/pci.h | 2 + > 13 files changed, 1046 insertions(+), 3 deletions(-) > --- > base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b > change-id: 20240727-qps615-e2894a38d36f > > Best regards, >
