On Thu, Aug 01, 2024 at 05:57:35PM +0000, Sergey Bostandzhyan wrote: > The R2S Plus is basically an R2S with additional eMMC. > > The eMMC configuration for the DTS has been extracted and copied from > rk3328-nanopi-r2.dts, v2017.09 branch from the friendlyarm/uboot-rockchip > repository. > > Signed-off-by: Sergey Bostandzhyan <jin@xxxxxxxxxxxx> > --- > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../dts/rockchip/rk3328-nanopi-r2s-plus.dts | 31 +++++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index fda1b980eb4b..36258dc8dafd 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s-plus.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts > new file mode 100644 > index 000000000000..7b83090a2145 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2018 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyarm.com) > + * > + * (C) Copyright 2016 Rockchip Electronics Co., Ltd > + */ > + > +/dts-v1/; > +#include "rk3328-nanopi-r2s.dts" > + > +/ { > + model = "FriendlyElec NanoPi R2S Plus"; > + compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328"; > + > + aliases { > + mmc1 = &emmc; > + }; > +}; > + > +&emmc { > + bus-width = <8>; > + cap-mmc-highspeed; > + supports-emmc; > + disable-wp; > + non-removable; > + num-slots = <1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; I think it's worth adding mmc-hs200-1_8v; I've tried getting the best speed possible and while HS400 with and without enhanced strobe did NOT work, hs200 works just fine. [ 0.459863] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0) [ 0.460884] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0) ... [ 0.728220] dwmmc_rockchip ff520000.mmc: Successfully tuned phase to 194 [ 0.728940] mmc1: new HS200 MMC card at address 0001 [ 0.730774] mmcblk1: mmc1:0001 A3A551 28.9 GiB [ 0.733262] mmcblk1: p1 p2 [ 0.734562] mmcblk1boot0: mmc1:0001 A3A551 4.00 MiB [ 0.736818] mmcblk1boot1: mmc1:0001 A3A551 4.00 MiB [ 0.738503] mmcblk1rpmb: mmc1:0001 A3A551 16.0 MiB, chardev (245:0) root@OpenWrt:/# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 342 MB in 3.00 seconds = 113.81 MB/sec Without 'mmc-hs200-1_8v' property in DT the eMMC is detected as [ 0.440465] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0) [ 0.442032] mmc1: new high speed MMC card at address 0001 [ 0.444261] mmcblk1: mmc1:0001 A3A551 28.9 GiB [ 0.447388] mmcblk1: p1 p2 [ 0.448744] mmcblk1boot0: mmc1:0001 A3A551 4.00 MiB [ 0.451065] mmcblk1boot1: mmc1:0001 A3A551 4.00 MiB [ 0.452871] mmcblk1rpmb: mmc1:0001 A3A551 16.0 MiB, chardev (245:0) root@OpenWrt:/# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 134 MB in 3.03 seconds = 44.18 MB/sec > + status = "okay"; > +}; I'm right now trying to get SDIO RTL8822CS working, so far I'm out of luck, but it can be added later once we got it working.
