On Thu, Jul 25, 2024 at 01:16:07PM +0100, pierre-henry.moussay@xxxxxxxxxxxxx wrote: > From: Pierre-Henry Moussay <pierre-henry.moussay@xxxxxxxxxxxxx> > > Add device tree bindings for the Microchip PIC64GX system > clock controller > > Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@xxxxxxxxxxxxx> I don't see a point in duplicating this header from mpfs. The defines are all identical. Cheers, Conor. > --- > .../clock/microchip,pic64gx-clock.h | 76 +++++++++++++++++++ > 1 file changed, 76 insertions(+) > create mode 100644 include/dt-bindings/clock/microchip,pic64gx-clock.h > > diff --git a/include/dt-bindings/clock/microchip,pic64gx-clock.h b/include/dt-bindings/clock/microchip,pic64gx-clock.h > new file mode 100644 > index 000000000000..91687c9da516 > --- /dev/null > +++ b/include/dt-bindings/clock/microchip,pic64gx-clock.h > @@ -0,0 +1,76 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Daire McNamara,<daire.mcnamara@xxxxxxxxxxxxx> > + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_ > +#define _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_ > + > +#define CLK_CPU 0 > +#define CLK_AXI 1 > +#define CLK_AHB 2 > + > +#define CLK_ENVM 3 > +#define CLK_MAC0 4 > +#define CLK_MAC1 5 > +#define CLK_MMC 6 > +#define CLK_TIMER 7 > +#define CLK_MMUART0 8 > +#define CLK_MMUART1 9 > +#define CLK_MMUART2 10 > +#define CLK_MMUART3 11 > +#define CLK_MMUART4 12 > +#define CLK_SPI0 13 > +#define CLK_SPI1 14 > +#define CLK_I2C0 15 > +#define CLK_I2C1 16 > +#define CLK_CAN0 17 > +#define CLK_CAN1 18 > +#define CLK_USB 19 > +#define CLK_RESERVED 20 > +#define CLK_RTC 21 > +#define CLK_QSPI 22 > +#define CLK_GPIO0 23 > +#define CLK_GPIO1 24 > +#define CLK_GPIO2 25 > +#define CLK_DDRC 26 > +#define CLK_FIC0 27 > +#define CLK_FIC1 28 > +#define CLK_FIC2 29 > +#define CLK_FIC3 30 > +#define CLK_ATHENA 31 > +#define CLK_CFM 32 > + > +#define CLK_RTCREF 33 > +#define CLK_MSSPLL 34 > +#define CLK_MSSPLL0 34 > +#define CLK_MSSPLL1 35 > +#define CLK_MSSPLL2 36 > +#define CLK_MSSPLL3 37 > +/* 38 is reserved for MSS PLL internals */ > + > +/* Clock Conditioning Circuitry Clock IDs */ > + > +#define CLK_CCC_PLL0 0 > +#define CLK_CCC_PLL1 1 > +#define CLK_CCC_DLL0 2 > +#define CLK_CCC_DLL1 3 > + > +#define CLK_CCC_PLL0_OUT0 4 > +#define CLK_CCC_PLL0_OUT1 5 > +#define CLK_CCC_PLL0_OUT2 6 > +#define CLK_CCC_PLL0_OUT3 7 > + > +#define CLK_CCC_PLL1_OUT0 8 > +#define CLK_CCC_PLL1_OUT1 9 > +#define CLK_CCC_PLL1_OUT2 10 > +#define CLK_CCC_PLL1_OUT3 11 > + > +#define CLK_CCC_DLL0_OUT0 12 > +#define CLK_CCC_DLL0_OUT1 13 > + > +#define CLK_CCC_DLL1_OUT0 14 > +#define CLK_CCC_DLL1_OUT1 15 > + > +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_ */ > -- > 2.30.2 >
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