On Sat, Jul 20, 2024 at 12:01:58PM +0000, Harry Austen wrote: > Xilinx clocking wizard IP core's dynamic reconfiguration support is > optionally enabled at build time. Add a devicetree boolean property to > describe whether the hardware supports this feature or not. > > Signed-off-by: Harry Austen <hpausten@xxxxxxxxxxxxxx> > --- > .../devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > index 4609bb56b06b5..890aeebf6f375 100644 > --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -40,6 +40,12 @@ properties: > - const: s_axi_aclk > > > + xlnx,dynamic-reconfig: > + type: boolean The type here should be "flag" not boolean, boolean can be set to "false" and what you're likely doing is just checking for the property being present. "flag" doesn't allow false. > + description: > + Indicate whether the core has been configured with support for dynamic > + runtime reconfguration of the clocking primitive MMCM/PLL. > + > xlnx,speed-grade: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [1, 2, 3] > @@ -88,6 +94,7 @@ examples: > compatible = "xlnx,clocking-wizard-v6.0"; > reg = <0xb0000000 0x10000>; > #clock-cells = <1>; > + xlnx,dynamic-reconfig; > xlnx,speed-grade = <1>; > xlnx,nr-outputs = <6>; > clock-names = "clk_in1", "s_axi_aclk"; > -- > 2.45.2 > >
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