This series adds support for the clock and reset controller in the Nuvoton WPCM450 SoC. This means that the clock rates for peripherals will be calculated automatically based on the clock tree as it was preconfigured by the bootloader. The 24 MHz dummy clock, that is currently in the devicetree, is no longer needed. Somewhat unfortunately, this also means that there is a breaking change once the devicetree starts relying on the clock driver, but I find it acceptable in this case, because WPCM450 is still at a somewhat early stage. v12: - Convert to platform driver, but use fixed-factor-clock for timer (a necessary workaround because npcm7xx-timer needs its clock earlier than a platform driver can provide it) - Various driver improvements suggested or inspired by Stephen Boyd - New patches: - clk: Introduce devm_clk_hw_register_divider_table_parent_data() - clk: provider: Address documentation pitfall in struct clk_parent_data v11: - Link: https://lore.kernel.org/r/20240401-wpcm-clk-v11-0-379472961244@xxxxxxx - Improved description in "ARM: dts: wpcm450: Remove clock-output-names from reference clock node" - some minor format differences due to switching to B4 v10: - A small tweak (using selected instead of extending an already-long default line) in Kconfig, for better robustness v9: - Various improvements to the driver - No longer use global clock names (and the clock-output-names property) to refer to the reference clock, but instead rely on a phandle reference v8: - https://lore.kernel.org/lkml/20230428190226.1304326-1-j.neuschaefer@xxxxxxx/ - Use %pe throughout the driver v7: - Simplified the error handling, by largely removing resource deallocation, which: - was already incomplete - would only happen in a case when the system is in pretty bad state because the clock driver didn't initialize correctly (in other words, the clock driver isn't optional enough that complex error handling really pays off) v6: - Dropped all patches except the clock binding and the clock driver, because they have mostly been merged - Minor correction to how RESET_SIMPLE is selected v5: - Dropped patch 2 (watchdog: npcm: Enable clock if provided), which was since merged upstream - Added patch 2 (clocksource: timer-npcm7xx: Enable timer 1 clock before use) again, because I wasn't able to find it in linux-next - Switched the driver to using struct clk_parent_data - Rebased on 6.1-rc3 v4: - Leave WDT clock running during after restart handler - Fix reset controller initialization - Dropped patch 2/7 (clocksource: timer-npcm7xx: Enable timer 1 clock before use), as it was applied by Daniel Lezcano v3: - https://lore.kernel.org/lkml/20220508194333.2170161-1-j.neuschaefer@xxxxxxx/ - Changed "refclk" string to "ref" - Fixed some dead code in the driver - Added clk_prepare_enable call to the watchdog restart handler - Added a few review tags v2: - https://lore.kernel.org/lkml/20220429172030.398011-1-j.neuschaefer@xxxxxxx/ - various small improvements v1: - https://lore.kernel.org/lkml/20220422183012.444674-1-j.neuschaefer@xxxxxxx/ Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> --- --- Jonathan Neuschäfer (6): dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller clk: Introduce devm_clk_hw_register_divider_table_parent_data() clk: provider: Address documentation pitfall in struct clk_parent_data clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver ARM: dts: wpcm450: Remove clock-output-names from reference clock node ARM: dts: wpcm450: Switch clocks to clock controller .../bindings/clock/nuvoton,wpcm450-clk.yaml | 65 +++ arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 33 +- drivers/clk/Makefile | 2 +- drivers/clk/nuvoton/Kconfig | 10 +- drivers/clk/nuvoton/Makefile | 1 + drivers/clk/nuvoton/clk-wpcm450.c | 455 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++ include/linux/clk-provider.h | 26 +- 8 files changed, 643 insertions(+), 16 deletions(-) --- base-commit: 4cece764965020c22cff7665b18a012006359095 change-id: 20240330-wpcm-clk-222a37f59cfb Best regards, -- Jonathan Neuschäfer <j.neuschaefer@xxxxxxx>
