Add CCU and ETR device tree nodes to enable related functions. Signed-off-by: Jie Gan <quic_jiegan@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 163 ++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..ef4df5e59ab3 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1664,6 +1664,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + ccu@4001000 { + compatible = "qcom,coresight-ccu"; + reg = <0x0 0x4001000 0x0 0x1000>; + reg-names = "ccu-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccu_in0: endpoint { + qcom,ccu-atid-offset = <0xf8>; + remote-endpoint = + <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + ccu_in1: endpoint { + qcom,ccu-atid-offset = <0x108>; + remote-endpoint = + <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -1867,6 +1899,129 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = + <&etr_rep_in>; + }; + }; + }; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = + <&swao_rep_out0>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = + <&ccu_in0>; + }; + }; + }; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = + <&etr_rep_out0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_rep_out0: endpoint { + remote-endpoint = + <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + etr_rep_out1: endpoint { + remote-endpoint = + <&etr1_in>; + }; + }; + }; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = + <&qdss_rep_out0>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = + <&ccu_in1>; + }; + }; + }; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = + <&etr_rep_out1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -1942,6 +2097,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + swao_rep_out0: endpoint { + remote-endpoint = + <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint { -- 2.34.1