On 27/06/2024 18:13, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Document the device tree bindings for the Renesas RZ/V2H(P) SoC > Clock Pulse Generator (CPG). > > CPG block handles the below operations: > - Generation and control of clock signals for the IP modules > - Generation and control of resets > - Control over booting > - Low power consumption and power supply domains > > Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the > core clocks are a subset of the ones which are listed as part of section > 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
