implemented basic spi support for TH1520 SoC.
created a fixed clock and a simple spi0 node.
updated the matching binding to include thead,th1520-spi as compatible.
added a spidev device in devicetree which will utilise the spi0 node.
this is usually reserved for a SPI NOR flash which is left unpopulated
underneath the carrier board. I performed a SPI self loop test using
tools/spi/spidev_test.c and tried sending `\xDE\xAD\xBE\xEF` and verified
it is being received correctly. i updated the of_device_id struct in
drivers/spi/spi-dw-mmio.c to include "thead,th1520-spi" as the compatible.
this patch also adds basic spi support on beaglev ahead which shares the
same TH1520 SoC. i have only tested on LicheePi 4A.
Signed-off-by: Kanak Shilledar <kanakshilledar@xxxxxxxxx>
---
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
.../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++
.../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 10 ++++++++++
arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++
drivers/spi/spi-dw-mmio.c | 1 +
6 files changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index fde3776a558b..bccd00a1ddd0 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -88,6 +88,10 @@ properties:
- renesas,r9a06g032-spi # RZ/N1D
- renesas,r9a06g033-spi # RZ/N1S
- const: renesas,rzn1-spi # RZ/N1
+ - description: T-HEAD TH1520 SoC SPI Controller
+ items:
+ - const: thead,th1520-spi
+ - const: snps,dw-apb-ssi
reg:
minItems: 1
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index d9b4de9e4757..3103b74e0288 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -17,6 +17,7 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ spi0 = &spi0;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -52,6 +53,10 @@ &sdhci_clk {
clock-frequency = <198000000>;
};
+&spi_clk {
+ clock-frequency = <396000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -79,3 +84,7 @@ &sdio0 {
&uart0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 1365d3a512a3..6939bd36560c 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -33,6 +33,10 @@ &sdhci_clk {
clock-frequency = <198000000>;
};
+&spi_clk {
+ clock-frequency = <396000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 9a3884a73e13..26f82fe91489 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -14,6 +14,7 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ spi0 = &spi0;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -30,3 +31,12 @@ chosen {
&uart0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index d2fa25839012..f962de663e7e 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -140,6 +140,12 @@ apb_clk: apb-clk-clock {
#clock-cells = <0>;
};
+ spi_clk: spi-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "spi_clk";
+ #clock-cells = <0>;
+ };
+
uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-output-names = "uart_sclk";
@@ -183,6 +189,16 @@ clint: timer@ffdc000000 {
<&cpu3_intc 3>, <&cpu3_intc 7>;
};
+ spi0: spi@ffe700c000 {
+ compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spi_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 819907e332c4..39e3d46ebf5d 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -419,6 +419,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
{ .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
+ { .compatible = "thead,th1520-spi", .data = dw_spi_pssi_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
--
2.45.2
