Stephen Warren <swarren@xxxxxxxxxxxxx> writes: > On 03/02/2015 01:54 PM, Eric Anholt wrote: >> From: Lubomir Rintel <lkundrak@xxxxx> >> >> Implement BCM2835 mailbox support as a device registered with the >> general purpose mailbox framework. Implementation based on commits by >> Lubomir Rintel [1], Suman Anna and Jassi Brar [2] on which to base the >> implementation. > >> diff --git a/drivers/mailbox/bcm2835-mailbox.c b/drivers/mailbox/bcm2835-mailbox.c > >> +/* Mailboxes */ >> +#define ARM_0_MAIL0 0x00 >> +#define ARM_0_MAIL1 0x20 >> + >> +/* >> + * Mailbox registers. We basically only support mailbox 0 & 1. We >> + * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See >> + * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about >> + * the placement of memory barriers. >> + */ >> +#define MAIL0_RD (ARM_0_MAIL0 + 0x00) >> +#define MAIL0_POL (ARM_0_MAIL0 + 0x10) >> +#define MAIL0_STA (ARM_0_MAIL0 + 0x18) >> +#define MAIL0_CNF (ARM_0_MAIL0 + 0x1C) >> +#define MAIL1_WRT (ARM_0_MAIL1 + 0x00) > > That implies there are more mailboxes. I wonder if we should > parameterize which to use via some DT properties? I guess we can defer > that though; we can default to the current values and add properties > later if we want to use something else. BCM2835-ARM-Peripherals.pdf: "Default the interrupts from doorbell 0,1 and mailbox 0 go to the ARM this means that these resources should be written by the GPU and read by the ARM. The opposite holds for doorbells 2, 3 and mailbox 1." I don't see any references to more mailboxes than 0 and 1.
Attachment:
signature.asc
Description: PGP signature
