On 24/06/2024 10:19, Jacobe Zang wrote:
> Khadas Edge2 uses the PCI-e Ampak AP6275P 2T2R Wi-Fi 6 module.
>
> Co-developed-by: Muhammed Efe Cetin <efectn@xxxxxxxxxxxxxx>
> Signed-off-by: Muhammed Efe Cetin <efectn@xxxxxxxxxxxxxx>
> Signed-off-by: Jacobe Zang <jacobe.zang@xxxxxxxxxx>
> ---
> .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
> index 3b6286461a746..f674deb6f7da8 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
> @@ -356,6 +356,22 @@ &pcie2x1l2 {
> reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
> vpcie3v3-supply = <&vcc3v3_pcie_wl>;
> status = "okay";
> +
> + pcie@0,0 {
> + reg = <0x400000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + device_type = "pci";
> + bus-range = <0x40 0x4f>;
Isn't bus-range a property of PCI host bridge, so the parent? This is a
PCI device, right?
> +
> + wifi: wifi@0,0 {
Binding does not say anything about this. Rockchip PCI controller is the
PCI host bridge, isn't it? Then the pci@0,0 is the child, so what is this?
> + reg = <0x410000 0 0 0 0>;
> + clocks = <&hym8563>;
> + clock-names = "32k";
1. Bindings are before the users.
2. Where is the compatible? Are you sure this validates?
> + };
> + };
> +
No need for this blank line.
> };
>
> &pwm11 {
Best regards,
Krzysztof
