> +static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,
> + u32 port, u32 queue, u32 val)
> +{
> + u32 orig_val, tmp, all_rsv, fq_limit;
> + const u32 pse_port_oq_id[] = {
> + PSE_PORT0_QUEUE,
> + PSE_PORT1_QUEUE,
> + PSE_PORT2_QUEUE,
> + PSE_PORT3_QUEUE,
> + PSE_PORT4_QUEUE,
> + PSE_PORT5_QUEUE,
> + PSE_PORT6_QUEUE,
> + PSE_PORT7_QUEUE,
> + PSE_PORT8_QUEUE,
> + PSE_PORT9_QUEUE,
> + PSE_PORT10_QUEUE
> + };
> +static void airoha_fe_oq_rsv_init(struct airoha_eth *eth)
> +{
> + int i;
> +
> + /* hw misses PPE2 oq rsv */
> + airoha_fe_set(eth, REG_FE_PSE_BUF_SET,
> + PSE_DEF_RSV_PAGE * PSE_PORT8_QUEUE);
> +
> + for (i = 0; i < PSE_PORT0_QUEUE; i++)
> + airoha_fe_set_pse_oq_rsv(eth, 0, i, 0x40);
> + for (i = 0; i < PSE_PORT1_QUEUE; i++)
> + airoha_fe_set_pse_oq_rsv(eth, 1, i, 0x40);
> +
> + for (i = 6; i < PSE_PORT2_QUEUE; i++)
> + airoha_fe_set_pse_oq_rsv(eth, 2, i, 0);
> +
> + for (i = 0; i < PSE_PORT3_QUEUE; i++)
> + airoha_fe_set_pse_oq_rsv(eth, 3, i, 0x40);
Code like this is making me wounder about the split between MAC
driver, DSA driver and DSA tag driver. Or if it should actually be a
pure switchdev driver?
If there some open architecture documentation for this device?
What are these ports about?
> +static void airoha_qdma_clenaup_rx_queue(struct airoha_queue *q)
cleanup?
> +static int airoha_dev_open(struct net_device *dev)
> +{
> + struct airoha_eth *eth = netdev_priv(dev);
> + int err;
> +
> + if (netdev_uses_dsa(dev))
> + airoha_fe_set(eth, REG_GDM1_INGRESS_CFG, GDM1_STAG_EN_MASK);
> + else
> + airoha_fe_clear(eth, REG_GDM1_INGRESS_CFG, GDM1_STAG_EN_MASK);
Does that imply both instances of the GMAC are not connected to the
switch? Can one be used with a PHY?
Andrew
