On 06/17/2024, André Draszik wrote: > Some versions of this IP have been integrated using separate PMU power > control registers for the HS and SS parts. One example is the Google > Tensor gs101 SoC. > > Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their > exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value. > > The existing 'usbdrdphy' alias can not be used in this case because > that is meant for determining the correct PMU offset if multiple > distinct PHYs exist in the system (as opposed to one PHY with multiple > isolators). > > Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx> Tested-by: Will McVicker <willmcvicker@xxxxxxxxxx> [...] Thanks, Will
