On 6/19/24 5:40 PM, Christophe ROULLIER wrote:
On 6/19/24 15:14, Marek Vasut wrote:
On 6/19/24 9:41 AM, Christophe ROULLIER wrote:
Hi,
+static int stm32mp2_configure_syscfg(struct
plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ u32 reg = dwmac->mode_reg;
+ int val = 0;
+
+ switch (plat_dat->mac_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ break;
dwmac->enable_eth_ck does not apply to MII mode ? Why ?
It is like MP1 and MP13, nothing to set in syscfg register for
case MII mode wo crystal.
Have a look at STM32MP15xx RM0436 Figure 83. Peripheral clock
distribution for Ethernet.
If RCC (top-left corner of the figure) generates 25 MHz MII clock
(yellow line) on eth_clk_fb (top-right corner), can I set
ETH_REF_CLK_SEL to position '1' and ETH_SEL[2] to '0' and feed ETH
(right side) clk_rx_i input with 25 MHz clock that way ?
I seems like this should be possible, at least theoretically. Can
you check with the hardware/silicon people ?
No it is not possible (it will work if speed (and frequency) is
fixed 25Mhz=100Mbps, but for speed 10Mbps (2,5MHz) it will not work.
Could the pll4_p_ck or pll3_q_ck generate either 25 MHz or 2.5 MHz
as needed in that case ? Then it would work, right ?
Yes you can set frequency you want for pll4 or pll3, if you set 25MHz
and auto-negotiation of speed is 100Mbps it should work (pad ETH_CK
of 25MHz clock the PHY and eth_clk_fb set to 25MHz for clk_RX)
but if autoneg of speed is 10Mbps, then 2.5MHz is needed for clk_RX
(you will provide 25Mhz)
What if:
- Aneg is 10 Mbps
- PLL4_P_CK/PLL3_Q_CK = 2.5 MHz
- ETH_REF_CLK_SEL = 1
- ETH_SEL[2] = 0
?
Then, clk_rx_i is 2.5 MHz, right ?
Yes that right
Does this configuration work ?
For me no, because PHY Ethernet Oscillator/cristal need in PAD 25Mhz or
50Mhz, I think it is does not work if oscillator frequency provided is
2.5MHz (To my knowledge there is no Ethernet PHY which have oscillator
working to 2.5MHz)
Would it work if the PHY had a dedicated Xtal , while the clocking of
the MAC was done using RCC ?
