Am Montag, 17. Juni 2024, 23:48:12 CEST schrieb Cristian Ciocaltea:
> The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
> CRU. It provides more accurate clock rates required by VOP2 to improve
> existing support for display modes handling, which is known to be
> problematic when dealing with non-integer refresh rates, among others.
>
> It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
> used to support HDMI 2.1 4K@120Hz mode.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 189 +++++++++++++++++++---
> 1 file changed, 167 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 72de287282eb..ad3fd4084377 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> static int rk_hdptx_phy_power_on(struct phy *phy)
> {
> struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
> int bus_width = phy_get_bus_width(hdptx->phy);
> + int ret;
> +
> /*
> * FIXME: Temporary workaround to pass pixel_clk_rate
> * from the HDMI bridge driver until phy_configure_opts_hdmi
> @@ -871,20 +925,18 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
> dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
> __func__, bus_width, rate);
>
> - return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
> + ret = rk_hdptx_phy_consumer_get(hdptx, rate);
> + if (!ret)
> + ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
I think this will need a put if _mode_config fails?
> +
> + return ret;
> }
Heiko
