The HDMI PHY PLL can be used as an alternative clock source to RK3588
SoC CRU. Since it provides more accurate clock rates, it can be used by
VOP2 to improve display modes handling, such as supporting non-integer
refresh rates.
The first two patches in the series provide a couple of fixes and
improvements to the existing HDPTX PHY driver, while the next two add
the necessary changes to support the clock provider functionality.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
---
Cristian Ciocaltea (4):
phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h
phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level
dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add #clock-cells
phy: phy-rockchip-samsung-hdptx: Add clock provider support
.../bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 3 +
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 208 +++++++++++++++++----
2 files changed, 174 insertions(+), 37 deletions(-)
---
base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
change-id: 20240617-rk3588-hdmiphy-clkprov-f05f165ac029
