On PolarFire SoC, for performance reasons, we want to use non-coherent
DMA. Add it to the match table with the non-standard non-coherent
cache ops requirement.
Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
drivers/cache/sifive_ccache.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index 6874b72ec59d8..277e66a61efdc 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -122,6 +122,8 @@ static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu740-c000-ccache" },
{ .compatible = "starfive,jh7100-ccache",
.data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
+ { .compatible = "microchip,mpfs-ccache",
+ .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
{ .compatible = "sifive,ccache0" },
{ /* end of table */ }
};
--
2.43.2
