On 30.05.2024 20:38, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> This patch introduces function pointers, oen_read() and oen_write(), in the
> struct rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
> register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before
> writing to the PFC_OEN register is necessary, and the PFC_OEN register has
> more bits compared to the RZ/G2L family. To handle these differences
> between RZ/G2L and RZ/V2H(P) and to reuse the existing code for RZ/V2H(P),
> these function pointers are introduced.
>
> Additionally, this patch populates these function pointers with appropriate
> data for existing SoCs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> # on RZ/G3S
> ---
> v2->v3
> - Renamed read_oen->oen_read
> - Renamed write_oen->oen_write
> - Updated commit message
>
> RFC->v2
> - No change
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index f8a1a1f2eebe..807851c33e48 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -255,6 +255,8 @@ struct rzg2l_pinctrl_data {
> unsigned int n_variable_pin_cfg;
> void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
> void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
> + u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
> + int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
> };
>
> /**
> @@ -1035,7 +1037,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
> break;
>
> case PIN_CONFIG_OUTPUT_ENABLE:
> - arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
> + arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
> if (!arg)
> return -EINVAL;
> break;
> @@ -1144,7 +1146,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
>
> case PIN_CONFIG_OUTPUT_ENABLE:
> arg = pinconf_to_config_argument(_configs[i]);
> - ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
> + ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
> if (ret)
> return ret;
> break;
> @@ -2623,6 +2625,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
> #endif
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> .pmc_writeb = &rzg2l_pmc_writeb,
> + .oen_read = &rzg2l_read_oen,
> + .oen_write = &rzg2l_write_oen,
> };
>
> static struct rzg2l_pinctrl_data r9a07g044_data = {
> @@ -2636,6 +2640,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
> .hwcfg = &rzg2l_hwcfg,
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> .pmc_writeb = &rzg2l_pmc_writeb,
> + .oen_read = &rzg2l_read_oen,
> + .oen_write = &rzg2l_write_oen,
> };
>
> static struct rzg2l_pinctrl_data r9a08g045_data = {
> @@ -2648,6 +2654,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
> .hwcfg = &rzg3s_hwcfg,
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> .pmc_writeb = &rzg2l_pmc_writeb,
> + .oen_read = &rzg2l_read_oen,
> + .oen_write = &rzg2l_write_oen,
> };
>
> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
