On 30.05.2024 20:38, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Introduces pmc_writeb() function pointer, in the struct rzg2l_pinctrl_data
> to facilitate writing to the PMC register. On the RZ/V2H(P) SoC, unlocking
> the PWPR.REGWE_A bit before writing to PMC registers is required, whereas
> this is not the case for the existing RZ/G2L family. This addition enables
> the reuse of existing code for RZ/V2H(P). Additionally, this patch
> populates this function pointer with appropriate data for existing SoCs.
>
> Note that this functionality is only handled in rzg2l_gpio_request(), as
> PMC unlock/lock during PFC setup will be taken care of in the
> pwpr_pfc_lock_unlock() function pointer.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> # on RZ/G3S
> ---
> v2->v3
> - Now passing offset to pmc_writeb() instead of virtual address
>
> RFC->v2
> - No change
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index a3fd14b95c5a..f8a1a1f2eebe 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -254,6 +254,7 @@ struct rzg2l_pinctrl_data {
> const u64 *variable_pin_cfg;
> unsigned int n_variable_pin_cfg;
> void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
> + void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
> };
>
> /**
> @@ -383,6 +384,11 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
> };
> #endif
>
> +static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
> +{
> + writeb(val, pctrl->base + offset);
> +}
> +
> static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> u8 pin, u8 off, u8 func)
> {
> @@ -1329,7 +1335,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
> /* Select GPIO mode in PMC Register */
> reg8 = readb(pctrl->base + PMC(off));
> reg8 &= ~BIT(bit);
> - writeb(reg8, pctrl->base + PMC(off));
> + pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
>
> spin_unlock_irqrestore(&pctrl->lock, flags);
>
> @@ -2616,6 +2622,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
> .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
> #endif
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> + .pmc_writeb = &rzg2l_pmc_writeb,
> };
>
> static struct rzg2l_pinctrl_data r9a07g044_data = {
> @@ -2628,6 +2635,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
> ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
> .hwcfg = &rzg2l_hwcfg,
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> + .pmc_writeb = &rzg2l_pmc_writeb,
> };
>
> static struct rzg2l_pinctrl_data r9a08g045_data = {
> @@ -2639,6 +2647,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
> .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
> .hwcfg = &rzg3s_hwcfg,
> .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
> + .pmc_writeb = &rzg2l_pmc_writeb,
> };
>
> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
