On Tue, Mar 26, 2024 at 2:14 AM Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> wrote: > > Hi Laurent, > > Am Montag, 25. März 2024, 21:49:24 CET schrieb Laurent Pinchart: > > Hi Alexander, > > > > On Mon, Mar 25, 2024 at 04:52:21PM +0100, Alexander Stein wrote: > > > Am Montag, 25. März 2024, 16:13:39 CET schrieb Laurent Pinchart: > > > > From: Paul Elder <paul.elder@xxxxxxxxxxxxxxxx> > > > > > > > > The ISP supports both CSI and parallel interfaces, where port 0 > > > > corresponds to the former and port 1 corresponds to the latter. Since > > > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > > > > receiver, set them both to port 1. > > > > > > > > Signed-off-by: Paul Elder <paul.elder@xxxxxxxxxxxxxxxx> > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > > > > --- > > > > Changes since v1: > > > > > > > > - Fix clock ordering > > > > - Add #address-cells and #size-cells to ports nodes > > > > --- > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++ > > > > 1 file changed, 50 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > index bfc5c81a5bd4..1d2670b91b53 100644 > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > @@ -1616,6 +1616,56 @@ isi_in_1: endpoint { > > > > }; > > > > }; > > > > > > > > + isp_0: isp@32e10000 { > > > > + compatible = "fsl,imx8mp-isp"; > > > > + reg = <0x32e10000 0x10000>; > > > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > > + clock-names = "isp", "aclk", "hclk"; > > > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > > > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > > > + assigned-clock-rates = <500000000>; > > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > > + fsl,blk-ctrl = <&media_blk_ctrl 0>; > > > > + status = "disabled"; > > > > + > > > > + ports { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + port@1 { > > > > + reg = <1>; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > + isp_1: isp@32e20000 { > > > > + compatible = "fsl,imx8mp-isp"; > > > > + reg = <0x32e20000 0x10000>; > > > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > > + clock-names = "isp", "aclk", "hclk"; > > > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > > > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > > > + assigned-clock-rates = <500000000>; > > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > > + fsl,blk-ctrl = <&media_blk_ctrl 1>; > > > > + status = "disabled"; > > > > + > > > > + ports { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + port@1 { > > > > + reg = <1>; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > > > The patch itself is okay. But you might not be able to > > > configure the parent of IMX8MP_CLK_MEDIA_ISP if dewarp is enabled before. > > > This is due to IMX8MP_CLK_MEDIA_ISP_ROOT being enabled in 'pgc_ispdwp' > > > power domain. Reparenting is not possible anymore in this case. > > > > Good point. > > > > > Something like > > > ---8<--- > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -1837,11 +1837,13 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > > > <&clk IMX8MP_CLK_MEDIA_APB>, > > > <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > > > <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > > > + <&clk IMX8MP_CLK_MEDIA_ISP>, > > > <&clk IMX8MP_VIDEO_PLL1>; > > > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > > > <&clk IMX8MP_SYS_PLL1_800M>, > > > <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > - <&clk IMX8MP_VIDEO_PLL1_OUT>; > > > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > + <&clk IMX8MP_SYS_PLL2_500M>; > > > assigned-clock-rates = <500000000>, <200000000>, > > > <0>, <0>, <1039500000>; > > According to the i.MX8MP Data sheet, the nominal speed for MEDIA_ISP_CLOCL_ROOT is 400MHZ with 500MHz being allowed in overdrive mode. I think this clock rate should drop to the nominal value of 400MHz and those boards who support overdrive can increase it to 500MHz to avoid stiability issues and/or running out of spec. I created an imx8mm and imx8mn-overdrive.dtsi file. If there is interest, I can do the same for the 8MP as well. I haven't gone through all the clocks to determine if/what clocks are being overdriven. > > With an assigned clock rate here too then ? > > You are right. This posted diff is what I was using for a while now though. > Apparently the clock frequency was still correct. > > Best regards, > Alexander > > > > #power-domain-cells = <1>; > > > ---8<--- > > > is needed. > > > > Sascha, are you OK with this approach ? This patch appears to have gone stale. Is there any way we can push this forward? Thanks, adam > > > > > > dewarp: dwe@32e30000 { > > > > compatible = "nxp,imx8mp-dw100"; > > > > reg = <0x32e30000 0x10000>; > > > > > > > > base-commit: 4cece764965020c22cff7665b18a012006359095 > > > > > > > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > http://www.tq-group.com/ > >