Both QCP and CRD boards using X Elite (x1e80100) make use of 3 USB Type-C ports (USB1 SS0, SS1, and SS2). Describe the graph for the USB part of each one of them for now. The DP port will come at a later stage since there are some muxes/retimers involved, depending on the type of board. Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> --- Changes in v2: - Rebased on today's -next which already defines parts of the graph in SoC file. - Described the connectors for the CRD, like Konrad suggested. - Dropped the remote endpoints assignments from board files as they are already described in SoC file. - Re-worded the commit message to talk about the plural w.r.t. DP ports. - Link to v1: https://lore.kernel.org/r/20240527-x1e80100-dts-pmic-glink-v1-0-7ea5c8eb4d2b@xxxxxxxxxx --- Abel Vesa (3): arm64: dts: qcom: x1e80100: Add remote endpoints between PHYs and DPs arm64: dts: qcom: x1e80100-crd: Add pmic-glink node with all 3 connectors arm64: dts: qcom: x1e80100-qcp: Add pmic-glink node with all 3 connectors arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 122 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 119 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 9 +++ 3 files changed, 250 insertions(+) --- base-commit: ee78a17615ad0cfdbbc27182b1047cd36c9d4d5f change-id: 20231214-x1e80100-dts-pmic-glink-65e351579b8b Best regards, -- Abel Vesa <abel.vesa@xxxxxxxxxx>
