On 04/06/2024 11:52, Siddharth Vadapalli wrote: > The SERDES0 and SERDES1 instances of SERDES on J722S are single lane > SERDES which are individually muxed across different peripherals. > > LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is > muxed between PCIe and CPSW. > > Define the lane-muxing macros to be used as the idle state values. > > Co-developed-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx>
