Hi Prabhakar, Thanks for your patch! Please drop "driver" from the one-line summary. On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Document the device tree bindings of the Renesas RZ/V2H(P) SoC s/of/for/ > Clock Pulse Generator (CPG). > > CPG block handles the below operations: > - Handles the generation and control of clock signals for the IP modules Please drop "Handles the" > - The generation and control of resets Please drop "The". > - Control over booting > - Low power consumption and the power supply domains Please drop "the". > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml > @@ -0,0 +1,78 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > + > +description: | > + On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles the generation SoCs > + and control of clock signals for the IP modules, the generation and control of resets, > + and control over booting, low power consumption and the power supply domains. Please drop "the". > + > +properties: > + compatible: > + const: renesas,r9a09g057-cpg > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + description: > + Clock source to CPG can be either from external clock input (EXCLK) or > + crystal oscillator (XIN/XOUT). > + const: extal According to Figure 4.4-1 ("CPG Functional Block Diagram"), there are 3 (RTC, audio, main). > + > + '#clock-cells': > + description: | > + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" > + and a core clock reference, as defined in > + <dt-bindings/clock/r9a09g057-cpg.h>, > + - For module clocks, the two clock specifier cells must be "CPG_MOD" and > + a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>. > + const: 2 I understand this will be changed to 1, the clock number? > + '#power-domain-cells': > + description: > + SoC devices that are part of the CPG/Module Standby Mode Clock Domain and > + can be power-managed through Module Standby should refer to the CPG device > + node in their "power-domains" property, as documented by the generic PM > + Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. > + The power domain specifiers defined in <dt-bindings/clock/r9a09g057-cpg.h> could > + be used to reference individual CPG power domains. The latter suggests "const: 1". But the example below uses zero, as does the code? > + > + '#reset-cells': > + description: > + The single reset specifier cell must be the module number, as defined in reset number (or index). > + <dt-bindings/clock/r9a09g057-cpg.h>. > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#power-domain-cells' > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + cpg: clock-controller@10420000 { > + compatible = "renesas,r9a09g057-cpg"; > + reg = <0x10420000 0x10000>; > + clocks = <&extal_clk>; > + clock-names = "extal"; > + #clock-cells = <2>; > + #power-domain-cells = <0>; > + #reset-cells = <1>; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
