On Fri, May 31, 2024 at 08:00:32PM +0300, Abel Vesa wrote: > So the PCIe 6 can be configured in 4-lane mode or 2-lane mode. For > 4-lane mode, it fetches the lanes provided by PCIe 6b. For 2-lane mode, > PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure > it in 4-lane mode and then each board can configure it depending on the > design. Both the QCP and CRD boards, currently upstream, use the 6a for > NVMe in 4-lane mode. Also, mark the controller as 4-lane as well. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index fe7ca2a73f9d..17e4c5cda22d 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2838,7 +2838,7 @@ pcie6a: pci@1bf8000 { > dma-coherent; > > linux,pci-domain = <7>; > - num-lanes = <2>; > + num-lanes = <4>; > > interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, > @@ -2903,19 +2903,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > }; > > pcie6a_phy: phy@1bfc000 { > - compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; > - reg = <0 0x01bfc000 0 0x2000>; > + compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; > + reg = <0 0x01bfc000 0 0x2000>, > + <0 0x01bfe000 0 0x2000>; > > clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, > <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, > <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, > - <&gcc GCC_PCIE_6A_PIPE_CLK>; > + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; > clock-names = "aux", > "cfg_ahb", > "ref", > "rchng", > - "pipe"; > + "pipe", > + "pipediv2"; I see 5 clocks and 6 clock-names here. > > resets = <&gcc GCC_PCIE_6A_PHY_BCR>, > <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; > @@ -2927,6 +2929,8 @@ pcie6a_phy: phy@1bfc000 { > > power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; > > + qcom,4ln-config-sel = <&tcsr 0x1a000 0>; > + > #clock-cells = <0>; > clock-output-names = "pcie6a_pipe_clk"; > > > -- > 2.34.1 > -- With best wishes Dmitry