Currently, the PCIe 6a is being used on both upstream boards for NVMe in a 4-lane mode configuration, HW-wise. Fix the node accordingly to reflect the HW schematics and improve the performance. The phy counter part is here: https://lore.kernel.org/all/20240531-x1e80100-phy-add-gen4x4-v1-0-5c841dae7850@xxxxxxxxxx/ Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> --- Abel Vesa (2): arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHI arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode arch/arm64/boot/dts/qcom/x1e80100.dtsi | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) --- base-commit: 0e1980c40b6edfa68b6acf926bab22448a6e40c9 change-id: 20240531-x1e80100-dts-fixes-pcie6a-0cf5b75a818e Best regards, -- Abel Vesa <abel.vesa@xxxxxxxxxx>
