On 30/05/2024 13:51, Geert Uytterhoeven wrote:
> Hi Paul,
>
> On Fri, May 24, 2024 at 11:46 AM Paul Barker
> <paul.barker.ct@xxxxxxxxxxxxxx> wrote:
>> We currently support setting OEN (Output ENable) bits only for the
>> RZ/G3S SoC and so the functions rzg2l_oen_is_supported() and
>> rzg2l_pin_to_oen_bit() are hardcoded for the RZ/G3S. To prepare for
>> supporting OEN on SoCs in the RZ/G2L family, we need to make this code
>> more flexible.
>>
>> So, the rzg2l_oen_is_supported() and rzg2l_pin_to_oen_bit() functions
>> are replaced with a single translation function which is called via a
>> pin_to_oen_bit function pointer and returns an error code if OEN is not
>> supported for the given pin.
>>
>> Signed-off-by: Paul Barker <paul.barker.ct@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> @@ -256,6 +256,8 @@ struct rzg2l_pinctrl_data {
>> const struct rzg2l_hwcfg *hwcfg;
>> const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
>> unsigned int n_variable_pin_cfg;
>> + int (*pin_to_oen_bit)(const struct rzg2l_hwcfg *hwcfg,
>> + u32 caps, u32 offset, u8 pin);
>> };
>
> This definitely needs synchronization with Prabhakar, as he introduces
> a different set of function pointers to distinguish RZ/G2L (G3S) and
> RZ/V2H. We really like to end up with something that is consistent,
> and works for all.
Apologies that we missed this conflict!
We will have to use Prabhakar's approach. The methods for RZ/G2L &
RZ/G3S are similar enough to share read/write functions and just have
separate functions for determining which bit to set, but for RZ/V2H
we're writing to a completely different register.
So, please proceed with Prabhakar's patches. I'll rebase this series on
top of his and re-work the relevant bits.
Thanks,
--
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