Hi Ramon, On 24/05/24 11:42 pm, Ramón Nordin Rodriguez wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >>>>>> Is it doing this in an endless cycle? >>>>> >>>>> Exactly, so what I'm seeing is when the driver livelocks the macphy is >>>>> periodically pulling the irq pin low, the driver clears the interrupt >>>>> and repeat. >>>> If I understand correctly, you are keep on getting interrupt without >>>> indicating anything in the footer?. Are you using LAN8650 Rev.B0 or B1?. >>>> If it is B0 then can you try with Rev.B1 once? >>>> > > After a considerable ammount of headscratching it seems that disabling collision > detection on the macphy is the only way of getting it stable. > When PLCA is enabled it's expected that CD causes problems, when running > in CSMA/CD mode it was unexpected (for me at least). Thanks for the feedback. > > Disabling collision detection was discussed here > https://lore.kernel.org/netdev/20231127104045.96722-1-ramon.nordin.rodriguez@xxxxxxxxxxx/ As you started this thread long back, I thought that those patches are already in but now I understand that they are not. In all my testings I have my CD disable fix in my PHY driver. > in a patchset that I haven't gotten around to testing through properly > and fixing up, but now it's definetly a priority. > > Rev.b0 and b1 gives similar results in this domain, though I'm getting > lower throughput and it's easier/faster to get the internal error state > on rev.b1. > > When CD is disabled both chip revs seems stable in all of my testing. If I understand correctly, disabling CD when PLCA enabled works as expected in both B0 and B1? correct me if I am wrong. If that is the case, then I would recommend to concentrate on the below patch set to get in the mainline first instead of focusing on B1 patches which can be done after that. https://lore.kernel.org/netdev/20231127104045.96722-1-ramon.nordin.rodriguez@xxxxxxxxxxx/ > >>> >>> I'll check the footer content, thanks for the tip! >>> >>> All testing has bee done with Rev.B0, we've located a set of B1 chips. >>> So we'll get on resoldering and rerunning the test scenario. >> Thanks for the consideration. But be informed that the internal PHY >> initial settings are updated for the Rev.B1. But the one from the >> mainline still supports for Rev.B0. So that microchip_t1s.c to be >> updated to support Rev.B1. > > I posted a suggestion for how to bringup rev.b1 > https://lore.kernel.org/netdev/20240524140706.359537-1-ramon.nordin.rodriguez@xxxxxxxxxxx/ > > I should have prefaced the cover letter with 'ugly hacks ahead'. > >> >> Also I am in talk with our design team that whether the updated initial >> settings for B1 are also applicable for B0. If so, then we will have >> only one updated initial setting which supports both B0 and B1. > > Any update on this? I think, I have answered for this in another mail. > > I will submit a new revision of the lan8670 revc + disable collision > detection pathset where CD is disabled regardless of operating mode. Yes, I would recommend to do it. Best regards, Parthiban V > > R >
