> Il 16/05/24 13:14, Lorenzo Bianconi ha scritto: > > > Il 15/05/24 14:58, Lorenzo Bianconi ha scritto: > > > > Introduce reset binding definitions for reset controller available in > > > > the Airoha EN7581 clock module. > > > > > > > > Tested-by: Zhengping Zhang <zhengping.zhang@xxxxxxxxxx> > > > > Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> > > > > --- > > > > .../dt-bindings/reset/airoha,en7581-reset.h | 66 +++++++++++++++++++ > > > > 1 file changed, 66 insertions(+) > > > > create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h > > > > > > > > diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h > > > > new file mode 100644 > > > > index 000000000000..1b7ee62ed164 > > > > --- /dev/null > > > > +++ b/include/dt-bindings/reset/airoha,en7581-reset.h > > > > @@ -0,0 +1,66 @@ > > > > +// SPDX-License-Identifier: GPL-2.0-only > > > > +/* > > > > + * Copyright (c) 2024 AIROHA Inc > > > > + * Author: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> > > > > + */ > > > > + > > > > +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ > > > > +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ > > > > + > > > > +/* RST_CTRL2 */ > > > > +#define EN7581_XPON_PHY_RST 0 > > > > > > ** sarcasm mode on ** > > > > > > Count with me: 0... 1... 2... > > > > :) > > > > > > > > ** sarcasm mode off ** > > > > > > There's a jump here, you have a reset index 0 and an index 2, > > > but you're missing index 1, that's not right :-) > > > > > > Please fix. > > > > it is because BIT(1) is marked as 'reserved' in the documentation so I skipped it. > > Do you prefer to have it in that way? > > > > This is not my preference, it's rather a requirement for the bindings... > > That's why in the MediaTek reset controller part of the clk driver there is > a way to map those numbers (which are always sequential) to actual reset bits > in the controller... ack, fine. I will look into it. Thx for the pointer. Regards, Lorenzo > > Cheers! > > > Regards, > > Lorenzo > > > > > > > > Cheers, > > > Angelo > > > > > > > +#define EN7581_CPU_TIMER2_RST 2 > > > > +#define EN7581_HSUART_RST 3 > > > > +#define EN7581_UART4_RST 4 > > > > +#define EN7581_UART5_RST 5 > > > > +#define EN7581_I2C2_RST 6 > > > > +#define EN7581_XSI_MAC_RST 7 > > > > +#define EN7581_XSI_PHY_RST 8 > > > > +#define EN7581_NPU_RST 9 > > > > +#define EN7581_I2S_RST 10 > > > > +#define EN7581_TRNG_RST 11 > > > > +#define EN7581_TRNG_MSTART_RST 12 > > > > +#define EN7581_DUAL_HSI0_RST 13 > > > > +#define EN7581_DUAL_HSI1_RST 14 > > > > +#define EN7581_HSI_RST 15 > > > > +#define EN7581_DUAL_HSI0_MAC_RST 16 > > > > +#define EN7581_DUAL_HSI1_MAC_RST 17 > > > > +#define EN7581_HSI_MAC_RST 18 > > > > +#define EN7581_WDMA_RST 19 > > > > +#define EN7581_WOE0_RST 20 > > > > +#define EN7581_WOE1_RST 21 > > > > +#define EN7581_HSDMA_RST 22 > > > > +#define EN7581_TDMA_RST 24 > > > > +#define EN7581_EMMC_RST 25 > > > > +#define EN7581_SOE_RST 26 > > > > +#define EN7581_PCIE2_RST 27 > > > > +#define EN7581_XFP_MAC_RST 28 > > > > +#define EN7581_USB_HOST_P1_RST 29 > > > > +#define EN7581_USB_HOST_P1_U3_PHY_RST 30 > > > > +/* RST_CTRL1 */ > > > > +#define EN7581_PCM1_ZSI_ISI_RST 32 > > > > +#define EN7581_FE_PDMA_RST 33 > > > > +#define EN7581_FE_QDMA_RST 34 > > > > +#define EN7581_PCM_SPIWP_RST 36 > > > > +#define EN7581_CRYPTO_RST 38 > > > > +#define EN7581_TIMER_RST 40 > > > > +#define EN7581_PCM1_RST 43 > > > > +#define EN7581_UART_RST 44 > > > > +#define EN7581_GPIO_RST 45 > > > > +#define EN7581_GDMA_RST 46 > > > > +#define EN7581_I2C_MASTER_RST 48 > > > > +#define EN7581_PCM2_ZSI_ISI_RST 49 > > > > +#define EN7581_SFC_RST 50 > > > > +#define EN7581_UART2_RST 51 > > > > +#define EN7581_GDMP_RST 52 > > > > +#define EN7581_FE_RST 53 > > > > +#define EN7581_USB_HOST_P0_RST 54 > > > > +#define EN7581_GSW_RST 55 > > > > +#define EN7581_SFC2_PCM_RST 57 > > > > +#define EN7581_PCIE0_RST 58 > > > > +#define EN7581_PCIE1_RST 59 > > > > +#define EN7581_CPU_TIMER_RST 60 > > > > +#define EN7581_PCIE_HB_RST 61 > > > > +#define EN7581_XPON_MAC_RST 63 > > > > + > > > > +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ > > > >
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