Prajna, Mark, On Tue, May 14, 2024 at 11:45:08AM +0100, Prajna Rajendra Kumar wrote: > The SPI "hard" controller within the PolarFire SoC is capable of > handling eight CS lines, but only one CS line is wired. Therefore, use > GPIO descriptors to configure additional CS lines. > > Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@xxxxxxxxxxxxx> I provided an ack on v1, so here it is again: Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> In general you can keep tags between versions, if you intentionally drop tags you should mention why you dropped them. > --- > drivers/spi/spi-microchip-core.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c > index c10de45aa472..6246254e1dff 100644 > --- a/drivers/spi/spi-microchip-core.c > +++ b/drivers/spi/spi-microchip-core.c > @@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi) > struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); > u32 reg; > > + if (spi_is_csgpiod(spi)) > + return 0; Mark, This has no users outside of core code, but is < 6 months old. Is using it in a driver like this okay? Cheers, Conor. > + > /* > * Active high targets need to be specifically set to their inactive > * states during probe by adding them to the "control group" & thus > @@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev) > > host->num_chipselect = num_cs; > host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; > + host->use_gpio_descriptors = true; > host->setup = mchp_corespi_setup; > host->bits_per_word_mask = SPI_BPW_MASK(8); > host->transfer_one = mchp_corespi_transfer_one; > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
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