On 11/05/2024 20:19, Conor Dooley wrote: > > On Sat, May 11, 2024 at 03:02:56AM +0000, Xingyu Wu wrote: > > On 11/05/2024 05:05, Conor Dooley wrote: > > > > > > On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote: > > > > This patch is to add the notifier for PLL0 clock and set the PLL0 > > > > rate to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. > > > > > > > > The first patch is to add the notifier for PLL0 clock. Setting the > > > > PLL0 rate need the son clock (cpu_root) to switch its parent clock > > > > to OSC clock and switch it back after setting PLL0 rate. It need > > > > to use the cpu_root clock from SYSCRG and register the notifier in > > > > the SYSCRG driver. > > > > > > > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate > > > > to 1.5GHz to fix the problem about the lower rate of CPUfreq on > > > > the visionfive board. The cpu_core clock rate is set to 500MHz > > > > first to ensure that the cpu frequency will not suddenly become > > > > high and the cpu voltage is not enough to cause a crash when the PLL0 is set > to 1.5GHz. > > > > The cpu voltage and frequency are then adjusted together by CPUfreq. > > > > > > Hmm, how does sequencing work here? If we split the patches between > > > trees it sounds like without the dts patch, the clock tree would (or > > > could) crash, or mainline if the clock changes there before the dts > > > ones do. Am I misunderstanding that? > > > > Oh, I think you misunderstood it. Patch 1 (clock driver patch) does > > not cause the clock tree crash without the patch 2 (dts patch), and it > > just provides the correct flow of how to change the PLL0 rate. The > > patch 2 is to set the clock rate of cpu_core and PLL0 rate, which > > causes the crash without patch 1. Setting cpu_core rate is to avoid crashes by > insufficient cpu voltage when setting PLL0 rate. > > So is the problem in the other direction then? My dts tree will crash if I apply the > dts change without the clock patch? Sorry, I tested it and it could not crash using only dts patch. It can separate the patches and use it individually. > Additionally, what about U-Boot? Will it have problems if the dts is imported > there without changes to its clock driver? > It is not apply to U-Boot. In the U-Boot, the PLL0 rate should be 1GHz to for GMAC and PMIC to work. But now the PLL0 rate should be 1.5GHz in the Linux. Best regards, Xingyu Wu
