On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote: > This patch is to add the notifier for PLL0 clock and set the PLL0 rate > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. > > The first patch is to add the notifier for PLL0 clock. Setting the PLL0 > rate need the son clock (cpu_root) to switch its parent clock to OSC > clock and switch it back after setting PLL0 rate. It need to use the > cpu_root clock from SYSCRG and register the notifier in the SYSCRG > driver. > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to > 1.5GHz to fix the problem about the lower rate of CPUfreq on the > visionfive board. The cpu_core clock rate is set to 500MHz first to > ensure that the cpu frequency will not suddenly become high and the cpu > voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. > The cpu voltage and frequency are then adjusted together by CPUfreq. Hmm, how does sequencing work here? If we split the patches between trees it sounds like without the dts patch, the clock tree would (or could) crash, or mainline if the clock changes there before the dts ones do. Am I misunderstanding that?
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