On Thu, May 9, 2024 at 8:36 AM Shengjiu Wang <shengjiu.wang@xxxxxxx> wrote: > > Initialize audio PLL1 as the parent clock for 8kHz series rates, > audio PLL2 as the parent clock for 11kHz series rates. that PLL1 > and PLL2 can together support full range of audio sample rates. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx> Reviewed-by: Daniel Baluta <daniel.baluta@xxxxxxx>