On 5/3/24 14:20, Christian Marangi wrote:
Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
Acked-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx> -- Florian
Attachment:
smime.p7s
Description: S/MIME Cryptographic Signature
