This series hooks up the individual clocks for each pin controller in the gs101 DTS. On Google Tensor gs101 there are separate bus clocks / gates each for each pinctrl instance. To be able to access each pinctrl instance's registers, this bus clock needs to be running, otherwise register access will hang. The driver update to support this extra clock has been proposed in https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@xxxxxxxxxx This series depends on: * hsi2 series: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-0-f233be0a2455@xxxxxxxxxx * pin controller clock support: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@xxxxxxxxxx Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx> --- Changes in v2: - use <0> instead of a placeholder clock (Krzysztof) - Link to v1: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@xxxxxxxxxx --- André Draszik (4): arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl arch/arm64/boot/dts/exynos/google/gs101.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) --- base-commit: d04466706db5e241ee026f17b5f920e50dee26b5 change-id: 20240429-samsung-pinctrl-busclock-dts-46b223471541 Best regards, -- André Draszik <andre.draszik@xxxxxxxxxx>
