On 26.04.2024 8:34 PM, Connor Abbott wrote: > This isn't known to fix anything yet, but it's a good idea to add it. > > Signed-off-by: Connor Abbott <cwabbott0@xxxxxxxxx> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 4a3b12b20802..d88ec857f1cb 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1953,6 +1953,14 @@ static int hw_init(struct msm_gpu *gpu) > BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); > } > > + if (adreno_is_a750(adreno_gpu)) { > + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); "/* Disable ubwc merged UFC request feature */" > + > + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); "/* Enable TP flaghint and other performance settings */" > + } else if (adreno_is_a7xx(adreno_gpu)) { > + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); This is supposed to be bit(11) on !A750: "/* Disable non-ubwc read reqs from passing write reqs */" Konrad